apex signal, a division of nai, inc. 631.567.1100/631.567.1823(fax) 1-31-01 s 77 ld1 a001 rev b 1.2 170 wilbur place, bohemia, ny, 11716,usa www.naii.com / e-mail:sales@naii.com code:ovgu1 page 1 of 7 apex signal, a division of nai, inc . pc-77ld1 twelve (12) lvdt-to-digital converters ?programmable? tracking converters features: ? 16-bit resolution ? 0.025% fs accuracy ? continuous background bit testing with excitation and signal loss detection ? self-calibrating. does not require removal for calibration ? 360 hz to 10 khz operation ? autoranging input between 2.0 and 28 vrms ? 12, 8, and 4-channel versions available ? optional programmable reference excitation ? transformer isolated ? latch feature ? compensates for 60 phase shift ? no adjustments or trimming required ? part number, s/n, date code, and revision in permanent memory description: this high-density intelligent dsp-based card incorporates up to twelve (12) separate transformer isolated programmable lvdt/rvdt-to-digital tracking converters with extensive diagnostics, and optional programmable excitation supply. instead of buying cards that are set for specific inputs, the uniqueness of this design makes it possible to order our standard card that auto-ranges between 2.0 and 28 volts. operating frequency between 400 hz and 10 khz can be specified. each chanel is programmable for either 2 wire or 3,4 wire inputs. for 2 wire inputs, the output is computed as a/b (where a is the lvdt output and b is the excitation) and is expressed as % fs. for 3 or 4-wire devices, the output is computed as a-b/a+b and is expressed as %fs. this ratiometric technique assures that the output will change only when the lvdt position changes and will ignore excitation voltage variations. the latch feature permits the user to read all channels at the same time. reading will unlatch that channel. the converters utilize a type ii servo loop processing technique that enables tracking, at full accuracy, up to the specified maximum rate. intermediate transparent latches, on all data and velocity outputs, guarantee that current valid data is always available for any channel, without affecting the tracking performance of the converters. the optional on ? board excitation is field programmable. to simplify logistics, part number, s/n, date code, and revision are stored in permanent memory locations. this board incorporates major diagnostics that offer substantial improvements to system reliability because user is alerted to channel malfunction. three different tests (one on-line and two off-line) can be selected : the d2 test initiates automatic background bit testing. each channel is checked over the programmed signal range to a measuring accuracy 0.1% fs, and each signal and excitation is monitored. results are available in registers. the testing is totally transparent to the user, requires no external programming, has no effect on the standard operation of this card and can be enabled or disabled via the bus. the d3 test , if enabled, starts an initiated bit test that disconnects all channels from the outside world and connects them across an internal stimulus that generates and measures multiple voltages to a test accuracy of 0.1%fs. external excitation is not required. results can be read from registers. the testing requires no external programming and can be initiated or terminated via the bus.
apex signal, a division of nai, inc. 631.567.1100/631.567.1823(fax) 1-31-01 s 77 ld1 a001 rev b 1.2 170 wilbur place, bohemia, ny, 11716,usa www.naii.com / e-mail:sales@naii.com code:ovgu1 page 2 of 7 the d0 test is used to check the card and the pcbus interface. all channels are disconnected from the outside world, allowing the user to write any number of input positions to the card and then read the data from the interface. external excitation is not required. specifications: number of channels: 4, 8, or 12 (see part number) resolution: 16-bit accuracy: 0.025% fs bandwidth: 10% of excitation to 100 hz max. bw and tracking rate can easily be customized . input format: lvdt or rvdt input voltage autoranging from 2.0 to 28 vrms. transformer isolated. excitation voltage: not required for computation of output but should be connected to allow card to check for excitation loss. input impedance: 40 k ? min. at 360 hz frequency: specify between 360 hz to 10 khz, (see part number) phase shift: automatically compensates for phase shifts between the transducer excitation and output up to 60 (3 or 4-wire units ignore phase shift) wrap around self test: three powerful test methods are described in the programming instructions. power: + 5 vdc at 0.35 a 12 vdc at 0.1 a without excitation; 1.1 a for 5 va excitation output temperature, operating: 0c to +70c storage temperature: -45c to +85c. weight: 20 oz. excitation: optional (see part number). voltage: 2.0-28 vrms programmable (resolution 0.1 vrms) or 115 vrms fixed. accuracy 2%. frequency: 360 hz to 10 khz 1% with 1 hz resolution. regulation: 10% max., no load to full load. output power: 5 va max. at 40 min. inductive. principals of lvdt operation : typically, the lvdt primary is excited by an ac source, causing a magnetic flux to be generated within the transducer. voltages are induced in the two secondaries, with the magnitude varying with the position of the core. usually, the secondaries are connected in series opposition, causing a net output voltage of zero when the core is at the electrical center. when the core is displaced in either direction from center, the voltage increases linearly either in phase or out of phase with the excitation depending on the direction. interfacing the lvdt to the converter two common connection methods are: 1. primary as reference (two-wire system) this method of connection converts the widest range of lvdt sensors and. is the most sensitive to excitation voltage variations, as well as temperature and phase shift effects. 2. derived reference (three/four-wire lvdt) the lvdt is again excited from the primary side, but the converter reference is the sum of a + b that has constant amplitude for changing core displacement. this system is insensitive to temperature effects, phase shifts and oscillator instability and solves the identity (a-b)/(a+b)
apex signal, a division of nai, inc. 631.567.1100/631.567.1823(fax) 1-31-01 s 77 ld1 a001 rev b 1.2 170 wilbur place, bohemia, ny, 11716,usa www.naii.com / e-mail:sales@naii.com code:ovgu1 page 3 of 7 5.0 v 0.0 v 10.0 v position va -fs o vb +fs (usual lvdt configuration) (in-phase) va+vb=10v va+vb=10v va+vb=10v va-vb=10v va-vb=0v va-vb=10v va=0v va=5v va=10v vb=10v vb=5v vb=0v example uses 10vrms output various ldvt configurations 3 wire excitation a b a-b a+b a 4 wire excitation b 3 wire excitation a b a-b a+b lvdt connections: for 3,4 wire lvdt?s, connect a and b lvdt outputs to signal a and b inputs. excitation is not used but should be connected to enable card to sense and report any excitation loss. for 2 wire lvdt?s, connect a-b output of lvdt to card ?a? input and connect external excitation voltage to card ?b? input and excitation input. programming instructions: i/o configuration : this card requires 32 consecutive addresses in the i/o address space on a 32 byte boundary. the base address is switch settable in the 000-3e0 hex (0 to 992) address range . address= base + offset base a9 a8 a7 a6 a5 offset a4, a3, a2, a1, a0 decimal equiv. sw1* 32 sw2 ? 64 sw3 ? 128 sw4 ? 256 sw5 ? 512 ? ?1? = off ?0? = on note: base addresses to avoid: 378-37f parallel printer port 3b0-3bf monochrome display 3f8-3ff asynch comm 3f0-3f7 floppy disk 2 wire a - b
apex signal, a division of nai, inc. 631.567.1100/631.567.1823(fax) 1-31-01 s 77 ld1 a001 rev b 1.2 170 wilbur place, bohemia, ny, 11716,usa www.naii.com / e-mail:sales@naii.com code:ovgu1 page 4 of 7 page 1 (offset 1e = 0) 00 ch.1lo read 07 ch.4 hi read 0e ch. 8 lo read 15 ch.11 hi read 1c status , test lo read 01 ch.1 hi read 08 ch.5 lo read 0f ch. 8 hi read 16 ch.12 lo read 1d status , test hi read 02 ch.2 lo read 09 ch.5 hi read 10 ch. 9 lo read 17 ch.12 hi read 1e page register = 0 write 03 ch.2 hi read 0a ch.6 lo read 11 ch. 9 hi read 18 status , si g nal loss lo read 04 ch.3 lo read 0b ch.6 hi read 12 ch.10 lo read 19 status , si g nal loss hi read 05 ch.3 hi read 0c ch.7 lo read 13 ch.10 hi read 1a status , exc. loss lo read 06 ch.4lo read 0d ch.7 hi read 14 ch.11 lo read 1b status , exc. loss hi read page 2 (offset 1e = 1) 00 sig. ch.1 lo write/read 07 sig. ch.4 hi write/read 0e sig. ch.8 lo write/read 15 sig. ch.11 hi write/read 01 sig. ch.1 hi write/read 08 sig. ch.5 lo write/read 0f sig. ch.8 hi write/read 16 sig. ch.12 lo write/read 02 sig. ch.2 lo write/read 09 sig. ch.5 hi write/read 10 sig. ch.9 lo write/read 17 sig. ch.12 hi write/read 03 sig. ch.2 hi write/read 0a sig. ch.6 lo write/read 11 sig. ch.9 hi write/read 1e page register = 1 write 04 si g . ch.3 lo write/read 0b si g . ch.6 hi write/read 12 si g . ch.10 lo write/read 05 sig. ch.3 hi write/read 0c sig. ch.7 lo write/read 13 sig. ch.10 hi write/read 06 sig. ch.4 lo write/read 0d sig. ch.7 hi write/read 14 sig. ch.11 lo write/read page 6 (offset 1e = 5) 00 ( a+b ) ch.1 lo read 07 ( a+b ) ch.4 hi read 0e ( a+b ) ch.8 lo read 15 ( a+b ) ch.11 hi read 01 ( a+b ) ch.1 hi read 08 ( a+b ) ch.5 lo read 0f ( a+b ) ch.8 hi read 16 ( a+b ) ch.12 lo read 02 ( a+b ) ch.2 lo read 09 ( a+b ) ch.5 hi read 10 ( a+b ) ch. 9 lo read 17 ( a+b ) ch.12 hi read 03 ( a+b ) ch.2 hi read 0a ( a+b ) ch.6 lo read 11 ( a+b ) ch. 9 hi read 1e pa g e re g ister = 5 write 04 ( a+b ) ch.3 lo read 0b ( a+b ) ch.6 hi read 12 ( a+b ) ch.10 lo read 05 ( a+b ) ch.3 hi read 0c ( a+b ) ch.7 lo read 13 ( a+b ) ch.10 hi read 06 ( a+b ) ch.4 lo read 0d ( a+b ) ch.7 hi read 14 ( a+b ) ch.11 lo read page 7 (offset 1e = 6) 00 enable, test write/read 07 test position hiread/write 0c eo lo byte read/write 0f active ch. hi read/w r 02 test (d2) verify write/read 0a freq. lo byte read/write 0d eo hi b y te read/write 10 2or 3,4 wire input 06 test position lo read/write 0b freq. hi byte read/write 0e active ch. lo read/write 14 latch write 1e pa g e re g ister = 6 write page 8 (offset 1e = 7) 00 save write 0f p/n hi read 11 date code hi read 13 rev. level hi read 15 s/n hi read 0e p/n read 10 date code lo read 12 rev. level lo read 14 s/n lo read 1e pa g e re g ister = 7 hi byte lo byte d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 latch outputs xxxxxxxxxxxx xx1x test enable xxxxxxxxxxxxd3d2xd0 active channels xxxxch.12ch.11ch.10ch.9ch.8ch.7ch.6ch.5ch.4ch.3ch.2ch.1 status, signal xxxxch.12ch.11ch.10ch.9ch.8ch.7ch.6ch.5ch.4ch.3ch.2ch.1 status, excitation xxxxch.12ch.11ch.10ch.9ch.8ch.7ch.6ch.5ch.4ch.3ch.2ch.1 status, test xxxxch.12ch.11ch.10ch.9ch.8ch.7ch.6ch.5ch.4ch.3ch.2ch.1 2 or 3,4 wire input xxxxch.12ch.11ch.10ch.9ch.8ch.7ch.6ch.5ch.4ch.3ch.2ch.1 at power-on or system reset , all parameters are restored to last saved setup. enter active channels: set the bit, corresponding to each channel to be monitored during bit testing, in the active channel register at page 7, 0eh/0fh. ?1?=active; ?0?=not used. omitting this step will produce false alarms because unused channels will set faults. save setup: the current setup can be saved by writing 5555h to the save register at page 8, 00/01h. this location will automatically clear to 00/01h when the save is completed (within 5 seconds). when save is elected, all parameters are saved, however, any parameter can be changed at will. saving is optional. if not saved, reenter parameters at each power up. to restore factory shipped parameters, write aaaah to the save register at page 8, 00/01h, followed by system reset. note: after a save or restore, poll page 8, 00h and do not perform any other operation until word is at "0". data format: the output data is a-b/a+b and represents %fs. format is two's complement. max. positive excursion is 7fff, 0 = 0, and max. negative excursion is 8000.
apex signal, a division of nai, inc. 631.567.1100/631.567.1823(fax) 1-31-01 s 77 ld1 a001 rev b 1.2 170 wilbur place, bohemia, ny, 11716,usa www.naii.com / e-mail:sales@naii.com code:ovgu1 page 5 of 7 signal and reference the lvdt primary is energized by either the on-board excitation or from an external excitation. the 4-wire or 3-wire lvdt has two output voltages referred to as a and b. when connected to the a and b signal inputs no scaling is required because the inputs are autoranging, however the signal registers can be used to scale the output code. default settings for the signal registers at page 2 are ffffh. this results in a full scale output reading for full travel of the lvdt. a full scale output reading for less than full travel of the lvdt can be programmed by writing to the signal registers on page 2. for example, writing 8000h to page 2, 00/01h will result in channel 1 having a full scale output reading for one-half travel of the lvdt. for 2 wire inputs, the signal register can be used to adjust what fraction of the excitation voltage represents ?full travel? of the lvdt. optional reference supply: for frequency, write a 16-bit word ( ex: 400 hz = 1 1001 0000) at page 7, oah/obh. for voltage, write a word ( ex: 26.1 vrms = 1 0000 0101) with lsb = 0.1 vrms, to address page 7, och/odh . it is recommended that the user program the required frequency before setting the output voltage. selecting 2 or 3,4 wire operation: program the proper channel in the appropriate register on page 7,10h. logic 1 = 2 wire and logic 0 = 3,4 wire. read (a+b) output : : read binary number at appropriate register on page 6, and multiply by 0.01 volt. for 2 wire inputs, this represents the b voltage. latch: all channels may be latched by writing ?1? to d1 at page 7, 14h. reading channel will disengage latch. d2 test enable: writing ?1? to d2 at page 7, 00h initiates automatic background bit testing. each channel is checked over the programmed signal range to a measuring accuracy 0.1%fs, and each signal and excitation is monitored. the results are available in status registers. the testing is totally transparent to the user, requires no external programming, has no effect on the standard operation of this card and can be enabled or disabled via the bus. the card will write 55h to page 7, 02h when d2 is enabled. user can periodically clear to 0000h and then read page 7, 02h again, after 30 seconds, to verify that background bit testing is activated. status, test: check the corresponding bit of the test status register at page 1, 1ch/1dh for status of bit testing for each active channel. a ?1? = accuracy ok; ?0? = failed. (test cycle takes 45 seconds for accuracy error). status, exc: check the corresponding bit of the exc status register at page 1, 1ah/1bh for status of the excitation input for each active channel. a ?1? = exc. on, ?0? = exc. loss (excitation loss is detected after 2 seconds). status, sig: check the corresponding bit of the sig status register at page 1, 18h/19h for status of the input signals for each active channel. a "1" = signal on, ?0? = signal loss (signal loss is detected after 2 seconds). d3 test enable: writing ?1? to d3 of test register at page7, 00h, initiates a bit test that disconnects all channels from the outside world and connects them across an internal stimulus that generates multiple test voltages that are measured to a test accuracy of 0.1%fs. test cycle takes about 45 seconds and results can be read from the status registers when d3 changes from ?1? to ?0?. external excitation is not required. testing requires no external programming and can be initiated or terminated (by setting d3 to ?0?) via the bus. d0 test enable: checks the card and the pcbus interface. writing ?1? to d0 at page 7, 00h disconnects all channels from the outside world, allowing user to write any number of input positions to the card at page 7 06/07h and then read the data from the pcbus interface (allow 400 ms after writing). external excitation is not required. note: the do test will follow the program of channel 1: if channel 1 is programmed for 2 wire, then all channels will be tested in the 2 wire mode. if channel 1 is programmed for 3,4 wire, then all channels will be tested in the 3,4 wire mode. if the card is set up as a mix of 2 and 3,4 wire channels, then chan 1 must be set as 2 wire (and all channels will be tested with the appropriate channels passing ) and then chan 1 set as 3,4 wire ( and all channels will be tested with the appropriate channels passing ).
apex signal, a division of nai, inc. 631.567.1100/631.567.1823(fax) 1-31-01 s 77 ld1 a001 rev b 1.2 170 wilbur place, bohemia, ny, 11716,usa www.naii.com / e-mail:sales@naii.com code:ovgu1 page 6 of 7 front panel connector: j1 amp 748483-5 mate: amp 748368-1 pin ch.1 pin ch.2 pin ch.3 pin ch.4 pin ch.5 pin ch.6 pin ch.7 pin ch.8 pin ch.9 pin ch.10 39 sig. a lo 18 sig. a lo 36 sig. a lo 15 sig. a lo 33 sig. a lo 12 sig. a lo 30 sig. a lo 9 sig. a lo 27 sig. a lo 6 sig. a lo 78 sig. a hi 57 sig. a hi 75 sig. a hi 54 sig. a hi 72 sig. a hi 51 sig. a hi 69 sig. a hi 48 sig. a hi 66 sig. a hi 45 sig. a hi 58 sig. b hi 76 sig. b hi 55 sig. b hi 73 sig. b hi 52 sig. b hi 70 sig. b hi 49 sig. b hi 67 sig. b hi 46 sig. b hi 64 sig. b hi 19 sig. b lo 37 sig. b lo 16 sig. b lo 34 sig. b lo 13 sig. b lo 31 sig. b lo 10 sig. b lo 28 sig. b lo 7 sig. b lo 25 sig. b lo 38 exc. hi 17 exc. hi 35 exc. hi 14 exc. hi 32 exc. hi 11 exc. hi 29 exc. hi 8 exc. hi 26 exc. hi 5 exc. hi 77 exc. lo 56 exc. lo 74 exc. lo 53 exc. lo 71 exc. lo 50 exc. lo 68 exc. lo 47 exc. lo 65 exc. lo 44 exc. lo pin ch.11 pin ch.12 pin 24 sig. a lo 3 sig. a lo 59 latch + sig. a hi 42 sig. a hi 20 latch- 43 sig. b hi 61 sig. b hi 1 & 40 chassis 4 sig. b lo 22 sig. b lo 21 int. exc. out hi 23 exc. hi 2 exc. hi 60 int. exc. out lo 62 exc. lo 41 exc. lo do not connect to any undesignated pins. caution : the male mating connector can have dangerous voltages on the pins. be certain that power is turned off before removing the connector. code table code frequency (hz) notes 01 400 02 2.8k - 3.2k 03 2k 04 2.69k 05 3k
apex signal, a division of nai, inc. 631.567.1100/631.567.1823(fax) 1-31-01 s 77 ld1 a001 rev b 1.2 170 wilbur place, bohemia, ny, 11716,usa www.naii.com / e-mail:sales@naii.com code:ovgu1 page 7 of 7 part number designation 77ld1 - xx x x x x - xx total number of channels 04 = 4 channels code (see code table) 08 = 8 channels 12 = 12 channels environmental c = no conformal coating k = removable conformal coating isa bus 1 = 8-bit isa bus 2 = 16-bit isa bus options 0 = none 9 = custom design (see separate spec) excitation with on-board excitation supply: 1 = one common excitation input tied to the excitation supply 2 = individual excitation inputs without on-board excitation supply 3 = one common excitation input 4 = individual excitation inputs
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